a) Field of the Invention
The present invention relates to a semiconductor device manufacture method, and more particularly to a semiconductor device manufacture method with a process of patterning an aluminum containing wiring layer.
b) Description of the Related Art
Several methods are known for dry etching an aluminum containing wiring layer. Some of these methods will be described in the following. In this specification, "aluminum containing" is intended to mean aluminum or aluminum alloy.
In the first method, an aluminum containing conductive layer formed on a semiconductor substrate is etched by plasma of a mixed gas of BCl.sub.3 and Cl.sub.2 by using a resist pattern or the like as a mask. Both BCl.sub.3 and Cl.sub.2 produce Cl species in plasma. Cl species chemically react with an aluminum containing conductive layer and form volatile AlCl.sub.3 having a high vapor pressure. Dry etching of aluminum containing material is performed by evaporation and removal of AlCl.sub.3.
In the second method in JP-A-8-130206, as described, for example, aluminum containing material which also contains silicon deposited on a semiconductor substrate is etched by plasma of HCl gas. After main etching of an open space which is an opening having a low aspect ratio, aluminum containing material which also contains silicon and left in a narrow space which is an opening having a high aspect ratio is over-etched by increasing a flow rate of HCl gas.
An aspect ratio is defined as a fraction having a width as a denominator and a height as a numerator. Assuming that an opening has a constant height, the lower the aspect ratio, the broader the opening (open space), and the higher the aspect ratio, the narrower the opening (narrow space).
In the third method as disclosed in JP-A-6-295886, an aluminum containing conductive layer is dry etched by plasma of a mixed gas of HCl gas, chlorine containing gas (excepting HCl) such as Cl.sub.2, and N.sub.2 gas.
In order to make a semiconductor device highly integrated, it is necessary to layout wiring patterns densely. In order to lower the resistance of densely disposed wiring patterns, the height of each pattern is increased to have a larger cross sectional area of the wiring pattern. Etching an opening having a high aspect ratio is therefore necessary.
In the manufacture of semiconductor integrated circuit devices, high integration (fine patterning) and large diameter of semiconductor wafers are becoming common. With such technical advancements, low pressure and high density plasma is becoming a requisite for semiconductor fine processing techniques. In such plasma processing, efforts have been made to balance positive and negative charges of plasma in order to avoid adverse effects of charges injected from the plasma into a semiconductor substrate.
However, even if plasma having a uniform charge distribution on a flat surface is used, it is reported that charging damages peculiar to high density plasma, called electron shading damages, are formed if a resist mask is used which has an opening (narrow space) with a high aspect ratio.
In this specification, "electron shading damages" are intended to mean damages caused by excessive injection of positive charges in a conductive layer surface because electrons are shielded (shaded).
Electron shading damages are presumably formed by a motion difference between electrons and ions. Generally, a bias potential is generated between a semiconductor substrate and plasma so that ions having positive charges are incident upon the substrate while they are accelerated. In contrast, electrons having negative charges are decelerated by the electric field. As a result, ions are incident upon the substrate generally vertically, whereas electrons are incident upon the substrate obliquely with a large velocity component in the directions in parallel to the substrate surface.
If an insulating pattern is placed on the surface of a conductive material to be etched, obliquely incoming electrons are intercepted by the insulating pattern. However, vertically incoming ions are not intercepted by such an insulating pattern and are vertically incident upon the surface of the conductive material. From these reasons, excessive positive charges flow into the conductive material surface.
As electrons are captured in the side wall of the insulating pattern, an electric field is formed which repulses incident electrons. Most of electrons having a small kinetic energy in the vertical direction are repulsed or repelled. Electron shading damages are presumed to be formed in the manner described above.
Ions having positive charges are rather attracted by such an electric field and are assisted to enter the conductive material surface under the insulating pattern. If the conductive layer is electrically insulated from the substrate, positive charges are accumulated in the conductive layer under the insulating pattern. If the conductive layer is connected to an insulated gate electrode, an electric field is applied across the gate insulating film. If tunneling current flows through the gate insulating film by this electric field, it is supposed that positive charges accumulated in the conductive layer take a steady state. The gate insulating film is deteriorated by the tunneling current.
If the gate insulating film is thick, tunneling current is hard to flow therethrough. Therefore, the amount of positive charges accumulated in the conductive layer becomes large and an electric field is generated which attracts electrons to the surface of the conductive layer. As electrons are attracted by this electric field, this state becomes a steady state even if tunneling current does not flow.
As MOS transistors are made finer, the gate oxide film tends to become thinner. As the gate insulating film becomes thin, tunneling current becomes easy to flow and the lifetime of the gate insulating film is shortened by the tunnelling current caused by electron shading.
The first method using BCl.sub.3 /Cl.sub.2 forms electron shading damages if high density plasma is used.
The second method using two steps of etching by HCl forms a notch at the bottom of an etched aluminum containing wiring pattern on the substrate side, i.e., the cross section of the pattern is contracted at the bottom thereof (the line width is narrowed).
The third method using HCl/Cl.sub.2 /N.sub.2 is likely to form residue if N.sub.2 is added too much, or is likely to form side-etch if the amount of Cl.sub.2 is large and N.sub.2 is small. The residue may result in electrical short between wiring patterns or low reliability of wiring, and the side-etch may result in low patterning precision.